/**
  **************************************************************************************
  * @file    REG_ADC.h
  * @brief   ADC Header File
  *
  * @version V1.00.01
  * @date    04/12/2018
  * @author  Eastsoft MCU Software Team
  * @note
  *
  * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved.
  *
  **************************************************************************************
  */

#ifndef __ADC_H__
#define __ADC_H__


/******************************************************************************/
/*                              设备特殊寄存器结构定义                        */
/******************************************************************************/

/*   允许匿名结构和匿名联合    */
/* #pragma anon_unions */

/****************** Bit definition for ADC_CFG register ************************/

#define  ADC_CFG_TESTEN_POSS  8U 
#define  ADC_CFG_TESTEN_POSE  15U 
#define  ADC_CFG_TESTEN_MSK  BITS(ADC_CFG_TESTEN_POSS,ADC_CFG_TESTEN_POSE)

#define  ADC_CFG_MODE_POS  0U 
#define  ADC_CFG_MODE_MSK  BIT(ADC_CFG_MODE_POS)

/****************** Bit definition for ADC_SRATE register ************************/

#define  ADC_SRATE_CNT_POSS  16U 
#define  ADC_SRATE_CNT_POSE  23U 
#define  ADC_SRATE_CNT_MSK  BITS(ADC_SRATE_CNT_POSS,ADC_SRATE_CNT_POSE)

#define  ADC_SRATE_CNTINI_POSS  8U 
#define  ADC_SRATE_CNTINI_POSE  15U 
#define  ADC_SRATE_CNTINI_MSK  BITS(ADC_SRATE_CNTINI_POSS,ADC_SRATE_CNTINI_POSE)

#define  ADC_SRATE_CKDIV_POSS  1U 
#define  ADC_SRATE_CKDIV_POSE  4U 
#define  ADC_SRATE_CKDIV_MSK  BITS(ADC_SRATE_CKDIV_POSS,ADC_SRATE_CKDIV_POSE)

#define  ADC_SRATE_CKEN_POS  0U 
#define  ADC_SRATE_CKEN_MSK  BIT(ADC_SRATE_CKEN_POS)

/****************** Bit definition for ADC_CHINV register ************************/

#define  ADC_CHINV_CH15INV_POS  15U 
#define  ADC_CHINV_CH15INV_MSK  BIT(ADC_CHINV_CH15INV_POS)

#define  ADC_CHINV_CH14INV_POS  14U 
#define  ADC_CHINV_CH14INV_MSK  BIT(ADC_CHINV_CH14INV_POS)

#define  ADC_CHINV_CH13INV_POS  13U 
#define  ADC_CHINV_CH13INV_MSK  BIT(ADC_CHINV_CH13INV_POS)

#define  ADC_CHINV_CH12INV_POS  12U 
#define  ADC_CHINV_CH12INV_MSK  BIT(ADC_CHINV_CH12INV_POS)

#define  ADC_CHINV_CH11INV_POS  11U 
#define  ADC_CHINV_CH11INV_MSK  BIT(ADC_CHINV_CH11INV_POS)

#define  ADC_CHINV_CH10INV_POS  10U 
#define  ADC_CHINV_CH10INV_MSK  BIT(ADC_CHINV_CH10INV_POS)

#define  ADC_CHINV_CH9INV_POS  9U 
#define  ADC_CHINV_CH9INV_MSK  BIT(ADC_CHINV_CH9INV_POS)

#define  ADC_CHINV_CH8INV_POS  8U 
#define  ADC_CHINV_CH8INV_MSK  BIT(ADC_CHINV_CH8INV_POS)

#define  ADC_CHINV_CH7INV_POS  7U 
#define  ADC_CHINV_CH7INV_MSK  BIT(ADC_CHINV_CH7INV_POS)

#define  ADC_CHINV_CH6INV_POS  6U 
#define  ADC_CHINV_CH6INV_MSK  BIT(ADC_CHINV_CH6INV_POS)

#define  ADC_CHINV_CH5INV_POS  5U 
#define  ADC_CHINV_CH5INV_MSK  BIT(ADC_CHINV_CH5INV_POS)

#define  ADC_CHINV_CH4INV_POS  4U 
#define  ADC_CHINV_CH4INV_MSK  BIT(ADC_CHINV_CH4INV_POS)

#define  ADC_CHINV_CH3INV_POS  3U 
#define  ADC_CHINV_CH3INV_MSK  BIT(ADC_CHINV_CH3INV_POS)

#define  ADC_CHINV_CH2INV_POS  2U 
#define  ADC_CHINV_CH2INV_MSK  BIT(ADC_CHINV_CH2INV_POS)

#define  ADC_CHINV_CH1INV_POS  1U 
#define  ADC_CHINV_CH1INV_MSK  BIT(ADC_CHINV_CH1INV_POS)

#define  ADC_CHINV_CH0INV_POS  0U 
#define  ADC_CHINV_CH0INV_MSK  BIT(ADC_CHINV_CH0INV_POS)

/****************** Bit definition for ADC_GAINL register ************************/

#define  ADC_GAINL_CH7PGA_POSS  21U 
#define  ADC_GAINL_CH7PGA_POSE  23U 
#define  ADC_GAINL_CH7PGA_MSK  BITS(ADC_GAINL_CH7PGA_POSS,ADC_GAINL_CH7PGA_POSE)

#define  ADC_GAINL_CH6PGA_POSS  18U 
#define  ADC_GAINL_CH6PGA_POSE  20U 
#define  ADC_GAINL_CH6PGA_MSK  BITS(ADC_GAINL_CH6PGA_POSS,ADC_GAINL_CH6PGA_POSE)

#define  ADC_GAINL_CH5PGA_POSS  15U 
#define  ADC_GAINL_CH5PGA_POSE  17U 
#define  ADC_GAINL_CH5PGA_MSK  BITS(ADC_GAINL_CH5PGA_POSS,ADC_GAINL_CH5PGA_POSE)

#define  ADC_GAINL_CH4PGA_POSS  12U 
#define  ADC_GAINL_CH4PGA_POSE  14U 
#define  ADC_GAINL_CH4PGA_MSK  BITS(ADC_GAINL_CH4PGA_POSS,ADC_GAINL_CH4PGA_POSE)

#define  ADC_GAINL_CH3PGA_POSS  9U 
#define  ADC_GAINL_CH3PGA_POSE  11U 
#define  ADC_GAINL_CH3PGA_MSK  BITS(ADC_GAINL_CH3PGA_POSS,ADC_GAINL_CH3PGA_POSE)

#define  ADC_GAINL_CH2PGA_POSS  6U 
#define  ADC_GAINL_CH2PGA_POSE  8U 
#define  ADC_GAINL_CH2PGA_MSK  BITS(ADC_GAINL_CH2PGA_POSS,ADC_GAINL_CH2PGA_POSE)

#define  ADC_GAINL_CH1PGA_POSS  3U 
#define  ADC_GAINL_CH1PGA_POSE  5U 
#define  ADC_GAINL_CH1PGA_MSK  BITS(ADC_GAINL_CH1PGA_POSS,ADC_GAINL_CH1PGA_POSE)

#define  ADC_GAINL_CH0PGA_POSS  0U 
#define  ADC_GAINL_CH0PGA_POSE  2U 
#define  ADC_GAINL_CH0PGA_MSK  BITS(ADC_GAINL_CH0PGA_POSS,ADC_GAINL_CH0PGA_POSE)

/****************** Bit definition for ADC_GAINH register ************************/

#define  ADC_GAINH_CH15PGA_POSS  21U 
#define  ADC_GAINH_CH15PGA_POSE  23U 
#define  ADC_GAINH_CH15PGA_MSK  BITS(ADC_GAINH_CH15PGA_POSS,ADC_GAINH_CH15PGA_POSE)

#define  ADC_GAINH_CH14PGA_POSS  18U 
#define  ADC_GAINH_CH14PGA_POSE  20U 
#define  ADC_GAINH_CH14PGA_MSK  BITS(ADC_GAINH_CH14PGA_POSS,ADC_GAINH_CH14PGA_POSE)

#define  ADC_GAINH_CH13PGA_POSS  15U 
#define  ADC_GAINH_CH13PGA_POSE  17U 
#define  ADC_GAINH_CH13PGA_MSK  BITS(ADC_GAINH_CH13PGA_POSS,ADC_GAINH_CH13PGA_POSE)

#define  ADC_GAINH_CH12PGA_POSS  12U 
#define  ADC_GAINH_CH12PGA_POSE  14U 
#define  ADC_GAINH_CH12PGA_MSK  BITS(ADC_GAINH_CH12PGA_POSS,ADC_GAINH_CH12PGA_POSE)

#define  ADC_GAINH_CH11PGA_POSS  9U 
#define  ADC_GAINH_CH11PGA_POSE  11U 
#define  ADC_GAINH_CH11PGA_MSK  BITS(ADC_GAINH_CH11PGA_POSS,ADC_GAINH_CH11PGA_POSE)

#define  ADC_GAINH_CH10PGA_POSS  6U 
#define  ADC_GAINH_CH10PGA_POSE  8U 
#define  ADC_GAINH_CH10PGA_MSK  BITS(ADC_GAINH_CH10PGA_POSS,ADC_GAINH_CH10PGA_POSE)

#define  ADC_GAINH_CH9PGA_POSS  3U 
#define  ADC_GAINH_CH9PGA_POSE  5U 
#define  ADC_GAINH_CH9PGA_MSK  BITS(ADC_GAINH_CH9PGA_POSS,ADC_GAINH_CH9PGA_POSE)

#define  ADC_GAINH_CH8PGA_POSS  0U 
#define  ADC_GAINH_CH8PGA_POSE  2U 
#define  ADC_GAINH_CH8PGA_MSK  BITS(ADC_GAINH_CH8PGA_POSS,ADC_GAINH_CH8PGA_POSE)

/****************** Bit definition for ADC_FRF register ************************/

#define  ADC_FRF_FFRST_POS  4U 
#define  ADC_FRF_FFRST_MSK  BIT(ADC_FRF_FFRST_POS)

#define  ADC_FRF_SS3RF_POS  3U 
#define  ADC_FRF_SS3RF_MSK  BIT(ADC_FRF_SS3RF_POS)

#define  ADC_FRF_SS2RF_POS  2U 
#define  ADC_FRF_SS2RF_MSK  BIT(ADC_FRF_SS2RF_POS)

#define  ADC_FRF_SS1RF_POS  1U 
#define  ADC_FRF_SS1RF_MSK  BIT(ADC_FRF_SS1RF_POS)

#define  ADC_FRF_SS0RF_POS  0U 
#define  ADC_FRF_SS0RF_MSK  BIT(ADC_FRF_SS0RF_POS)

/****************** Bit definition for ADC_SSEN register ************************/

#define  ADC_SSEN_IDLE_POS  4U 
#define  ADC_SSEN_IDLE_MSK  BIT(ADC_SSEN_IDLE_POS)

#define  ADC_SSEN_SS3EN_POS  3U 
#define  ADC_SSEN_SS3EN_MSK  BIT(ADC_SSEN_SS3EN_POS)

#define  ADC_SSEN_SS2EN_POS  2U 
#define  ADC_SSEN_SS2EN_MSK  BIT(ADC_SSEN_SS2EN_POS)

#define  ADC_SSEN_SS1EN_POS  1U 
#define  ADC_SSEN_SS1EN_MSK  BIT(ADC_SSEN_SS1EN_POS)

#define  ADC_SSEN_SS0EN_POS  0U 
#define  ADC_SSEN_SS0EN_MSK  BIT(ADC_SSEN_SS0EN_POS)

/****************** Bit definition for ADC_SWTRI register ************************/

#define  ADC_SWTRI_SS3_POS  3U 
#define  ADC_SWTRI_SS3_MSK  BIT(ADC_SWTRI_SS3_POS)

#define  ADC_SWTRI_SS2_POS  2U 
#define  ADC_SWTRI_SS2_MSK  BIT(ADC_SWTRI_SS2_POS)

#define  ADC_SWTRI_SS1_POS  1U 
#define  ADC_SWTRI_SS1_MSK  BIT(ADC_SWTRI_SS1_POS)

#define  ADC_SWTRI_SS0_POS  0U 
#define  ADC_SWTRI_SS0_MSK  BIT(ADC_SWTRI_SS0_POS)

/****************** Bit definition for ADC_IER register ************************/

#define  ADC_IER_TOIE_POS  4U 
#define  ADC_IER_TOIE_MSK  BIT(ADC_IER_TOIE_POS)

#define  ADC_IER_SS3IE_POS  3U 
#define  ADC_IER_SS3IE_MSK  BIT(ADC_IER_SS3IE_POS)

#define  ADC_IER_SS2IE_POS  2U 
#define  ADC_IER_SS2IE_MSK  BIT(ADC_IER_SS2IE_POS)

#define  ADC_IER_SS1IE_POS  1U 
#define  ADC_IER_SS1IE_MSK  BIT(ADC_IER_SS1IE_POS)

#define  ADC_IER_SS0IE_POS  0U 
#define  ADC_IER_SS0IE_MSK  BIT(ADC_IER_SS0IE_POS)

/****************** Bit definition for ADC_IDR register ************************/

#define  ADC_IDR_TOID_POS  4U 
#define  ADC_IDR_TOID_MSK  BIT(ADC_IDR_TOID_POS)

#define  ADC_IDR_SS3ID_POS  3U 
#define  ADC_IDR_SS3ID_MSK  BIT(ADC_IDR_SS3ID_POS)

#define  ADC_IDR_SS2ID_POS  2U 
#define  ADC_IDR_SS2ID_MSK  BIT(ADC_IDR_SS2ID_POS)

#define  ADC_IDR_SS1ID_POS  1U 
#define  ADC_IDR_SS1ID_MSK  BIT(ADC_IDR_SS1ID_POS)

#define  ADC_IDR_SS0ID_POS  0U 
#define  ADC_IDR_SS0ID_MSK  BIT(ADC_IDR_SS0ID_POS)

/****************** Bit definition for ADC_IVS register ************************/

#define  ADC_IVS_TOIVS_POS  4U 
#define  ADC_IVS_TOIVS_MSK  BIT(ADC_IVS_TOIVS_POS)

#define  ADC_IVS_SS3IVS_POS  3U 
#define  ADC_IVS_SS3IVS_MSK  BIT(ADC_IVS_SS3IVS_POS)

#define  ADC_IVS_SS2IVS_POS  2U 
#define  ADC_IVS_SS2IVS_MSK  BIT(ADC_IVS_SS2IVS_POS)

#define  ADC_IVS_SS1IVS_POS  1U 
#define  ADC_IVS_SS1IVS_MSK  BIT(ADC_IVS_SS1IVS_POS)

#define  ADC_IVS_SS0IVS_POS  0U 
#define  ADC_IVS_SS0IVS_MSK  BIT(ADC_IVS_SS0IVS_POS)

/****************** Bit definition for ADC_RIF register ************************/

#define  ADC_RIF_TORIF_POS  4U 
#define  ADC_RIF_TORIF_MSK  BIT(ADC_RIF_TORIF_POS)

#define  ADC_RIF_SS3RIF_POS  3U 
#define  ADC_RIF_SS3RIF_MSK  BIT(ADC_RIF_SS3RIF_POS)

#define  ADC_RIF_SS2RIF_POS  2U 
#define  ADC_RIF_SS2RIF_MSK  BIT(ADC_RIF_SS2RIF_POS)

#define  ADC_RIF_SS1RIF_POS  1U 
#define  ADC_RIF_SS1RIF_MSK  BIT(ADC_RIF_SS1RIF_POS)

#define  ADC_RIF_SS0RIF_POS  0U 
#define  ADC_RIF_SS0RIF_MSK  BIT(ADC_RIF_SS0RIF_POS)

/****************** Bit definition for ADC_IFM register ************************/

#define  ADC_IFM_TOIFM_POS  4U 
#define  ADC_IFM_TOIFM_MSK  BIT(ADC_IFM_TOIFM_POS)

#define  ADC_IFM_SS3IFM_POS  3U 
#define  ADC_IFM_SS3IFM_MSK  BIT(ADC_IFM_SS3IFM_POS)

#define  ADC_IFM_SS2IFM_POS  2U 
#define  ADC_IFM_SS2IFM_MSK  BIT(ADC_IFM_SS2IFM_POS)

#define  ADC_IFM_SS1IFM_POS  1U 
#define  ADC_IFM_SS1IFM_MSK  BIT(ADC_IFM_SS1IFM_POS)

#define  ADC_IFM_SS0IFM_POS  0U 
#define  ADC_IFM_SS0IFM_MSK  BIT(ADC_IFM_SS0IFM_POS)

/****************** Bit definition for ADC_ICR register ************************/

#define  ADC_ICR_TOICR_POS  4U 
#define  ADC_ICR_TOICR_MSK  BIT(ADC_ICR_TOICR_POS)

#define  ADC_ICR_SS3ICR_POS  3U 
#define  ADC_ICR_SS3ICR_MSK  BIT(ADC_ICR_SS3ICR_POS)

#define  ADC_ICR_SS2ICR_POS  2U 
#define  ADC_ICR_SS2ICR_MSK  BIT(ADC_ICR_SS2ICR_POS)

#define  ADC_ICR_SS1ICR_POS  1U 
#define  ADC_ICR_SS1ICR_MSK  BIT(ADC_ICR_SS1ICR_POS)

#define  ADC_ICR_SS0ICR_POS  0U 
#define  ADC_ICR_SS0ICR_MSK  BIT(ADC_ICR_SS0ICR_POS)

/****************** Bit definition for ADC_DMA register ************************/

#define  ADC_DMA_SS3_DMAEN_POS  3U 
#define  ADC_DMA_SS3_DMAEN_MSK  BIT(ADC_DMA_SS3_DMAEN_POS)

#define  ADC_DMA_SS2_DMAEN_POS  2U 
#define  ADC_DMA_SS2_DMAEN_MSK  BIT(ADC_DMA_SS2_DMAEN_POS)

#define  ADC_DMA_SS1_DMAEN_POS  1U 
#define  ADC_DMA_SS1_DMAEN_MSK  BIT(ADC_DMA_SS1_DMAEN_POS)

#define  ADC_DMA_SS0_DMAEN_POS  0U 
#define  ADC_DMA_SS0_DMAEN_MSK  BIT(ADC_DMA_SS0_DMAEN_POS)

/****************** Bit definition for ADC_SS0_CON register ************************/

#define  ADC_SS0_CON_SEL_POSS  11U 
#define  ADC_SS0_CON_SEL_POSE  15U 
#define  ADC_SS0_CON_SEL_MSK  BITS(ADC_SS0_CON_SEL_POSS,ADC_SS0_CON_SEL_POSE)

#define  ADC_SS0_CON_TYP_POS  8U 
#define  ADC_SS0_CON_TYP_MSK  BIT(ADC_SS0_CON_TYP_POS)

#define  ADC_SS0_CON_PRI_POSS  4U 
#define  ADC_SS0_CON_PRI_POSE  5U 
#define  ADC_SS0_CON_PRI_MSK  BITS(ADC_SS0_CON_PRI_POSS,ADC_SS0_CON_PRI_POSE)

#define  ADC_SS0_CON_ONE_POS  0U 
#define  ADC_SS0_CON_ONE_MSK  BIT(ADC_SS0_CON_ONE_POS)

/****************** Bit definition for ADC_SS0_MUX0 register ************************/

#define  ADC_SS0_MUX0_MUX7_POSS  28U 
#define  ADC_SS0_MUX0_MUX7_POSE  31U 
#define  ADC_SS0_MUX0_MUX7_MSK  BITS(ADC_SS0_MUX0_MUX7_POSS,ADC_SS0_MUX0_MUX7_POSE)

#define  ADC_SS0_MUX0_MUX6_POSS  24U 
#define  ADC_SS0_MUX0_MUX6_POSE  27U 
#define  ADC_SS0_MUX0_MUX6_MSK  BITS(ADC_SS0_MUX0_MUX6_POSS,ADC_SS0_MUX0_MUX6_POSE)

#define  ADC_SS0_MUX0_MUX5_POSS  20U 
#define  ADC_SS0_MUX0_MUX5_POSE  23U 
#define  ADC_SS0_MUX0_MUX5_MSK  BITS(ADC_SS0_MUX0_MUX5_POSS,ADC_SS0_MUX0_MUX5_POSE)

#define  ADC_SS0_MUX0_MUX4_POSS  16U 
#define  ADC_SS0_MUX0_MUX4_POSE  19U 
#define  ADC_SS0_MUX0_MUX4_MSK  BITS(ADC_SS0_MUX0_MUX4_POSS,ADC_SS0_MUX0_MUX4_POSE)

#define  ADC_SS0_MUX0_MUX3_POSS  12U 
#define  ADC_SS0_MUX0_MUX3_POSE  15U 
#define  ADC_SS0_MUX0_MUX3_MSK  BITS(ADC_SS0_MUX0_MUX3_POSS,ADC_SS0_MUX0_MUX3_POSE)

#define  ADC_SS0_MUX0_MUX2_POSS  8U 
#define  ADC_SS0_MUX0_MUX2_POSE  11U 
#define  ADC_SS0_MUX0_MUX2_MSK  BITS(ADC_SS0_MUX0_MUX2_POSS,ADC_SS0_MUX0_MUX2_POSE)

#define  ADC_SS0_MUX0_MUX1_POSS  4U 
#define  ADC_SS0_MUX0_MUX1_POSE  7U 
#define  ADC_SS0_MUX0_MUX1_MSK  BITS(ADC_SS0_MUX0_MUX1_POSS,ADC_SS0_MUX0_MUX1_POSE)

#define  ADC_SS0_MUX0_MUX0_POSS  0U 
#define  ADC_SS0_MUX0_MUX0_POSE  3U 
#define  ADC_SS0_MUX0_MUX0_MSK  BITS(ADC_SS0_MUX0_MUX0_POSS,ADC_SS0_MUX0_MUX0_POSE)

/****************** Bit definition for ADC_SS0_MUX1 register ************************/

#define  ADC_SS0_MUX1_MUX15_POSS  28U 
#define  ADC_SS0_MUX1_MUX15_POSE  31U 
#define  ADC_SS0_MUX1_MUX15_MSK  BITS(ADC_SS0_MUX1_MUX15_POSS,ADC_SS0_MUX1_MUX15_POSE)

#define  ADC_SS0_MUX1_MUX14_POSS  24U 
#define  ADC_SS0_MUX1_MUX14_POSE  27U 
#define  ADC_SS0_MUX1_MUX14_MSK  BITS(ADC_SS0_MUX1_MUX14_POSS,ADC_SS0_MUX1_MUX14_POSE)

#define  ADC_SS0_MUX1_MUX13_POSS  20U 
#define  ADC_SS0_MUX1_MUX13_POSE  23U 
#define  ADC_SS0_MUX1_MUX13_MSK  BITS(ADC_SS0_MUX1_MUX13_POSS,ADC_SS0_MUX1_MUX13_POSE)

#define  ADC_SS0_MUX1_MUX12_POSS  16U 
#define  ADC_SS0_MUX1_MUX12_POSE  19U 
#define  ADC_SS0_MUX1_MUX12_MSK  BITS(ADC_SS0_MUX1_MUX12_POSS,ADC_SS0_MUX1_MUX12_POSE)

#define  ADC_SS0_MUX1_MUX11_POSS  12U 
#define  ADC_SS0_MUX1_MUX11_POSE  15U 
#define  ADC_SS0_MUX1_MUX11_MSK  BITS(ADC_SS0_MUX1_MUX11_POSS,ADC_SS0_MUX1_MUX11_POSE)

#define  ADC_SS0_MUX1_MUX10_POSS  8U 
#define  ADC_SS0_MUX1_MUX10_POSE  11U 
#define  ADC_SS0_MUX1_MUX10_MSK  BITS(ADC_SS0_MUX1_MUX10_POSS,ADC_SS0_MUX1_MUX10_POSE)

#define  ADC_SS0_MUX1_MUX9_POSS  4U 
#define  ADC_SS0_MUX1_MUX9_POSE  7U 
#define  ADC_SS0_MUX1_MUX9_MSK  BITS(ADC_SS0_MUX1_MUX9_POSS,ADC_SS0_MUX1_MUX9_POSE)

#define  ADC_SS0_MUX1_MUX8_POSS  0U 
#define  ADC_SS0_MUX1_MUX8_POSE  3U 
#define  ADC_SS0_MUX1_MUX8_MSK  BITS(ADC_SS0_MUX1_MUX8_POSS,ADC_SS0_MUX1_MUX8_POSE)

/****************** Bit definition for ADC_SS0_END register ************************/

#define  ADC_SS0_END_IE15_POS  23U 
#define  ADC_SS0_END_IE15_MSK  BIT(ADC_SS0_END_IE15_POS)

#define  ADC_SS0_END_IE14_POS  22U 
#define  ADC_SS0_END_IE14_MSK  BIT(ADC_SS0_END_IE14_POS)

#define  ADC_SS0_END_IE13_POS  21U 
#define  ADC_SS0_END_IE13_MSK  BIT(ADC_SS0_END_IE13_POS)

#define  ADC_SS0_END_IE12_POS  20U 
#define  ADC_SS0_END_IE12_MSK  BIT(ADC_SS0_END_IE12_POS)

#define  ADC_SS0_END_IE11_POS  19U 
#define  ADC_SS0_END_IE11_MSK  BIT(ADC_SS0_END_IE11_POS)

#define  ADC_SS0_END_IE10_POS  18U 
#define  ADC_SS0_END_IE10_MSK  BIT(ADC_SS0_END_IE10_POS)

#define  ADC_SS0_END_IE9_POS  17U 
#define  ADC_SS0_END_IE9_MSK  BIT(ADC_SS0_END_IE9_POS)

#define  ADC_SS0_END_IE8_POS  16U 
#define  ADC_SS0_END_IE8_MSK  BIT(ADC_SS0_END_IE8_POS)

#define  ADC_SS0_END_IE7_POS  15U 
#define  ADC_SS0_END_IE7_MSK  BIT(ADC_SS0_END_IE7_POS)

#define  ADC_SS0_END_IE6_POS  14U 
#define  ADC_SS0_END_IE6_MSK  BIT(ADC_SS0_END_IE6_POS)

#define  ADC_SS0_END_IE5_POS  13U 
#define  ADC_SS0_END_IE5_MSK  BIT(ADC_SS0_END_IE5_POS)

#define  ADC_SS0_END_IE4_POS  12U 
#define  ADC_SS0_END_IE4_MSK  BIT(ADC_SS0_END_IE4_POS)

#define  ADC_SS0_END_IE3_POS  11U 
#define  ADC_SS0_END_IE3_MSK  BIT(ADC_SS0_END_IE3_POS)

#define  ADC_SS0_END_IE2_POS  10U 
#define  ADC_SS0_END_IE2_MSK  BIT(ADC_SS0_END_IE2_POS)

#define  ADC_SS0_END_IE1_POS  9U 
#define  ADC_SS0_END_IE1_MSK  BIT(ADC_SS0_END_IE1_POS)

#define  ADC_SS0_END_IE0_POS  8U 
#define  ADC_SS0_END_IE0_MSK  BIT(ADC_SS0_END_IE0_POS)

#define  ADC_SS0_END_END_POSS  0U 
#define  ADC_SS0_END_END_POSE  3U 
#define  ADC_SS0_END_END_MSK  BITS(ADC_SS0_END_END_POSS,ADC_SS0_END_END_POSE)

/****************** Bit definition for ADC_SS0_FSTAT register ************************/

#define  ADC_SS0_FSTAT_OV_POS  11U 
#define  ADC_SS0_FSTAT_OV_MSK  BIT(ADC_SS0_FSTAT_OV_POS)

#define  ADC_SS0_FSTAT_FULL_POS  10U 
#define  ADC_SS0_FSTAT_FULL_MSK  BIT(ADC_SS0_FSTAT_FULL_POS)

#define  ADC_SS0_FSTAT_UV_POS  9U 
#define  ADC_SS0_FSTAT_UV_MSK  BIT(ADC_SS0_FSTAT_UV_POS)

#define  ADC_SS0_FSTAT_EMPTY_POS  8U 
#define  ADC_SS0_FSTAT_EMPTY_MSK  BIT(ADC_SS0_FSTAT_EMPTY_POS)

#define  ADC_SS0_FSTAT_HPTR_POSS  4U 
#define  ADC_SS0_FSTAT_HPTR_POSE  7U 
#define  ADC_SS0_FSTAT_HPTR_MSK  BITS(ADC_SS0_FSTAT_HPTR_POSS,ADC_SS0_FSTAT_HPTR_POSE)

#define  ADC_SS0_FSTAT_TPTR_POSS  0U 
#define  ADC_SS0_FSTAT_TPTR_POSE  3U 
#define  ADC_SS0_FSTAT_TPTR_MSK  BITS(ADC_SS0_FSTAT_TPTR_POSS,ADC_SS0_FSTAT_TPTR_POSE)

/****************** Bit definition for ADC_SS0_DATA register ************************/

#define  ADC_SS0_DATA_DATA_POSS  0U 
#define  ADC_SS0_DATA_DATA_POSE  11U 
#define  ADC_SS0_DATA_DATA_MSK  BITS(ADC_SS0_DATA_DATA_POSS,ADC_SS0_DATA_DATA_POSE)

/****************** Bit definition for ADC_SS1_CON register ************************/

#define  ADC_SS1_CON_SEL_POSS  11U 
#define  ADC_SS1_CON_SEL_POSE  15U 
#define  ADC_SS1_CON_SEL_MSK  BITS(ADC_SS1_CON_SEL_POSS,ADC_SS1_CON_SEL_POSE)

#define  ADC_SS1_CON_TYP_POS  8U 
#define  ADC_SS1_CON_TYP_MSK  BIT(ADC_SS1_CON_TYP_POS)

#define  ADC_SS1_CON_PRI_POSS  4U 
#define  ADC_SS1_CON_PRI_POSE  5U 
#define  ADC_SS1_CON_PRI_MSK  BITS(ADC_SS1_CON_PRI_POSS,ADC_SS1_CON_PRI_POSE)

#define  ADC_SS1_CON_ONE_POS  0U 
#define  ADC_SS1_CON_ONE_MSK  BIT(ADC_SS1_CON_ONE_POS)

/****************** Bit definition for ADC_SS1_MUX0 register ************************/

#define  ADC_SS1_MUX0_MUX7_POSS  28U 
#define  ADC_SS1_MUX0_MUX7_POSE  31U 
#define  ADC_SS1_MUX0_MUX7_MSK  BITS(ADC_SS1_MUX0_MUX7_POSS,ADC_SS1_MUX0_MUX7_POSE)

#define  ADC_SS1_MUX0_MUX6_POSS  24U 
#define  ADC_SS1_MUX0_MUX6_POSE  27U 
#define  ADC_SS1_MUX0_MUX6_MSK  BITS(ADC_SS1_MUX0_MUX6_POSS,ADC_SS1_MUX0_MUX6_POSE)

#define  ADC_SS1_MUX0_MUX5_POSS  20U 
#define  ADC_SS1_MUX0_MUX5_POSE  23U 
#define  ADC_SS1_MUX0_MUX5_MSK  BITS(ADC_SS1_MUX0_MUX5_POSS,ADC_SS1_MUX0_MUX5_POSE)

#define  ADC_SS1_MUX0_MUX4_POSS  16U 
#define  ADC_SS1_MUX0_MUX4_POSE  19U 
#define  ADC_SS1_MUX0_MUX4_MSK  BITS(ADC_SS1_MUX0_MUX4_POSS,ADC_SS1_MUX0_MUX4_POSE)

#define  ADC_SS1_MUX0_MUX3_POSS  12U 
#define  ADC_SS1_MUX0_MUX3_POSE  15U 
#define  ADC_SS1_MUX0_MUX3_MSK  BITS(ADC_SS1_MUX0_MUX3_POSS,ADC_SS1_MUX0_MUX3_POSE)

#define  ADC_SS1_MUX0_MUX2_POSS  8U 
#define  ADC_SS1_MUX0_MUX2_POSE  11U 
#define  ADC_SS1_MUX0_MUX2_MSK  BITS(ADC_SS1_MUX0_MUX2_POSS,ADC_SS1_MUX0_MUX2_POSE)

#define  ADC_SS1_MUX0_MUX1_POSS  4U 
#define  ADC_SS1_MUX0_MUX1_POSE  7U 
#define  ADC_SS1_MUX0_MUX1_MSK  BITS(ADC_SS1_MUX0_MUX1_POSS,ADC_SS1_MUX0_MUX1_POSE)

#define  ADC_SS1_MUX0_MUX0_POSS  0U 
#define  ADC_SS1_MUX0_MUX0_POSE  3U 
#define  ADC_SS1_MUX0_MUX0_MSK  BITS(ADC_SS1_MUX0_MUX0_POSS,ADC_SS1_MUX0_MUX0_POSE)

/****************** Bit definition for ADC_SS1_END register ************************/

#define  ADC_SS1_END_IE7_POS  15U 
#define  ADC_SS1_END_IE7_MSK  BIT(ADC_SS1_END_IE7_POS)

#define  ADC_SS1_END_IE6_POS  14U 
#define  ADC_SS1_END_IE6_MSK  BIT(ADC_SS1_END_IE6_POS)

#define  ADC_SS1_END_IE5_POS  13U 
#define  ADC_SS1_END_IE5_MSK  BIT(ADC_SS1_END_IE5_POS)

#define  ADC_SS1_END_IE4_POS  12U 
#define  ADC_SS1_END_IE4_MSK  BIT(ADC_SS1_END_IE4_POS)

#define  ADC_SS1_END_IE3_POS  11U 
#define  ADC_SS1_END_IE3_MSK  BIT(ADC_SS1_END_IE3_POS)

#define  ADC_SS1_END_IE2_POS  10U 
#define  ADC_SS1_END_IE2_MSK  BIT(ADC_SS1_END_IE2_POS)

#define  ADC_SS1_END_IE1_POS  9U 
#define  ADC_SS1_END_IE1_MSK  BIT(ADC_SS1_END_IE1_POS)

#define  ADC_SS1_END_IE0_POS  8U 
#define  ADC_SS1_END_IE0_MSK  BIT(ADC_SS1_END_IE0_POS)

#define  ADC_SS1_END_END_POSS  0U 
#define  ADC_SS1_END_END_POSE  2U 
#define  ADC_SS1_END_END_MSK  BITS(ADC_SS1_END_END_POSS,ADC_SS1_END_END_POSE)

/****************** Bit definition for ADC_SS1_FSTAT register ************************/

#define  ADC_SS1_FSTAT_OV_POS  11U 
#define  ADC_SS1_FSTAT_OV_MSK  BIT(ADC_SS1_FSTAT_OV_POS)

#define  ADC_SS1_FSTAT_FULL_POS  10U 
#define  ADC_SS1_FSTAT_FULL_MSK  BIT(ADC_SS1_FSTAT_FULL_POS)

#define  ADC_SS1_FSTAT_UV_POS  9U 
#define  ADC_SS1_FSTAT_UV_MSK  BIT(ADC_SS1_FSTAT_UV_POS)

#define  ADC_SS1_FSTAT_EMPTY_POS  8U 
#define  ADC_SS1_FSTAT_EMPTY_MSK  BIT(ADC_SS1_FSTAT_EMPTY_POS)

#define  ADC_SS1_FSTAT_HPTR_POSS  4U 
#define  ADC_SS1_FSTAT_HPTR_POSE  7U 
#define  ADC_SS1_FSTAT_HPTR_MSK  BITS(ADC_SS1_FSTAT_HPTR_POSS,ADC_SS1_FSTAT_HPTR_POSE)

#define  ADC_SS1_FSTAT_TPTR_POSS  0U 
#define  ADC_SS1_FSTAT_TPTR_POSE  3U 
#define  ADC_SS1_FSTAT_TPTR_MSK  BITS(ADC_SS1_FSTAT_TPTR_POSS,ADC_SS1_FSTAT_TPTR_POSE)

/****************** Bit definition for ADC_SS1_DATA register ************************/

#define  ADC_SS1_DATA_DATA_POSS  0U 
#define  ADC_SS1_DATA_DATA_POSE  11U 
#define  ADC_SS1_DATA_DATA_MSK  BITS(ADC_SS1_DATA_DATA_POSS,ADC_SS1_DATA_DATA_POSE)

/****************** Bit definition for ADC_SS2_CON register ************************/

#define  ADC_SS2_CON_SEL_POSS  11U 
#define  ADC_SS2_CON_SEL_POSE  15U 
#define  ADC_SS2_CON_SEL_MSK  BITS(ADC_SS2_CON_SEL_POSS,ADC_SS2_CON_SEL_POSE)

#define  ADC_SS2_CON_TYP_POS  8U 
#define  ADC_SS2_CON_TYP_MSK  BIT(ADC_SS2_CON_TYP_POS)

#define  ADC_SS2_CON_PRI_POSS  4U 
#define  ADC_SS2_CON_PRI_POSE  5U 
#define  ADC_SS2_CON_PRI_MSK  BITS(ADC_SS2_CON_PRI_POSS,ADC_SS2_CON_PRI_POSE)

#define  ADC_SS2_CON_ONE_POS  0U 
#define  ADC_SS2_CON_ONE_MSK  BIT(ADC_SS2_CON_ONE_POS)

/****************** Bit definition for ADC_SS2_MUX0 register ************************/

#define  ADC_SS2_MUX0_MUX3_POSS  12U 
#define  ADC_SS2_MUX0_MUX3_POSE  15U 
#define  ADC_SS2_MUX0_MUX3_MSK  BITS(ADC_SS2_MUX0_MUX3_POSS,ADC_SS2_MUX0_MUX3_POSE)

#define  ADC_SS2_MUX0_MUX2_POSS  8U 
#define  ADC_SS2_MUX0_MUX2_POSE  11U 
#define  ADC_SS2_MUX0_MUX2_MSK  BITS(ADC_SS2_MUX0_MUX2_POSS,ADC_SS2_MUX0_MUX2_POSE)

#define  ADC_SS2_MUX0_MUX1_POSS  4U 
#define  ADC_SS2_MUX0_MUX1_POSE  7U 
#define  ADC_SS2_MUX0_MUX1_MSK  BITS(ADC_SS2_MUX0_MUX1_POSS,ADC_SS2_MUX0_MUX1_POSE)

#define  ADC_SS2_MUX0_MUX0_POSS  0U 
#define  ADC_SS2_MUX0_MUX0_POSE  3U 
#define  ADC_SS2_MUX0_MUX0_MSK  BITS(ADC_SS2_MUX0_MUX0_POSS,ADC_SS2_MUX0_MUX0_POSE)

/****************** Bit definition for ADC_SS2_END register ************************/

#define  ADC_SS2_END_IE3_POS  11U 
#define  ADC_SS2_END_IE3_MSK  BIT(ADC_SS2_END_IE3_POS)

#define  ADC_SS2_END_IE2_POS  10U 
#define  ADC_SS2_END_IE2_MSK  BIT(ADC_SS2_END_IE2_POS)

#define  ADC_SS2_END_IE1_POS  9U 
#define  ADC_SS2_END_IE1_MSK  BIT(ADC_SS2_END_IE1_POS)

#define  ADC_SS2_END_IE0_POS  8U 
#define  ADC_SS2_END_IE0_MSK  BIT(ADC_SS2_END_IE0_POS)

#define  ADC_SS2_END_END_POSS  0U 
#define  ADC_SS2_END_END_POSE  1U 
#define  ADC_SS2_END_END_MSK  BITS(ADC_SS2_END_END_POSS,ADC_SS2_END_END_POSE)

/****************** Bit definition for ADC_SS2_FSTAT register ************************/

#define  ADC_SS2_FSTAT_OV_POS  11U 
#define  ADC_SS2_FSTAT_OV_MSK  BIT(ADC_SS2_FSTAT_OV_POS)

#define  ADC_SS2_FSTAT_FULL_POS  10U 
#define  ADC_SS2_FSTAT_FULL_MSK  BIT(ADC_SS2_FSTAT_FULL_POS)

#define  ADC_SS2_FSTAT_UV_POS  9U 
#define  ADC_SS2_FSTAT_UV_MSK  BIT(ADC_SS2_FSTAT_UV_POS)

#define  ADC_SS2_FSTAT_EMPTY_POS  8U 
#define  ADC_SS2_FSTAT_EMPTY_MSK  BIT(ADC_SS2_FSTAT_EMPTY_POS)

#define  ADC_SS2_FSTAT_HPTR_POSS  4U 
#define  ADC_SS2_FSTAT_HPTR_POSE  7U 
#define  ADC_SS2_FSTAT_HPTR_MSK  BITS(ADC_SS2_FSTAT_HPTR_POSS,ADC_SS2_FSTAT_HPTR_POSE)

#define  ADC_SS2_FSTAT_TPTR_POSS  0U 
#define  ADC_SS2_FSTAT_TPTR_POSE  3U 
#define  ADC_SS2_FSTAT_TPTR_MSK  BITS(ADC_SS2_FSTAT_TPTR_POSS,ADC_SS2_FSTAT_TPTR_POSE)

/****************** Bit definition for ADC_SS2_DATA register ************************/

#define  ADC_SS2_DATA_DATA_POSS  0U 
#define  ADC_SS2_DATA_DATA_POSE  11U 
#define  ADC_SS2_DATA_DATA_MSK  BITS(ADC_SS2_DATA_DATA_POSS,ADC_SS2_DATA_DATA_POSE)

/****************** Bit definition for ADC_SS3_CON register ************************/

#define  ADC_SS3_CON_SEL_POSS  11U 
#define  ADC_SS3_CON_SEL_POSE  15U 
#define  ADC_SS3_CON_SEL_MSK  BITS(ADC_SS3_CON_SEL_POSS,ADC_SS3_CON_SEL_POSE)

#define  ADC_SS3_CON_TYP_POS  8U 
#define  ADC_SS3_CON_TYP_MSK  BIT(ADC_SS3_CON_TYP_POS)

#define  ADC_SS3_CON_PRI_POSS  4U 
#define  ADC_SS3_CON_PRI_POSE  5U 
#define  ADC_SS3_CON_PRI_MSK  BITS(ADC_SS3_CON_PRI_POSS,ADC_SS3_CON_PRI_POSE)

#define  ADC_SS3_CON_ONE_POS  0U 
#define  ADC_SS3_CON_ONE_MSK  BIT(ADC_SS3_CON_ONE_POS)

/****************** Bit definition for ADC_SS3_MUX0 register ************************/

#define  ADC_SS3_MUX0_MUX0_POSS  0U 
#define  ADC_SS3_MUX0_MUX0_POSE  3U 
#define  ADC_SS3_MUX0_MUX0_MSK  BITS(ADC_SS3_MUX0_MUX0_POSS,ADC_SS3_MUX0_MUX0_POSE)

/****************** Bit definition for ADC_SS3_END register ************************/

#define  ADC_SS3_END_IE0_POS  8U 
#define  ADC_SS3_END_IE0_MSK  BIT(ADC_SS3_END_IE0_POS)

#define  ADC_SS3_END_END_POS  0U 
#define  ADC_SS3_END_END_MSK  BIT(ADC_SS3_END_END_POS)

/****************** Bit definition for ADC_SS3_FSTAT register ************************/

#define  ADC_SS3_FSTAT_OV_POS  11U 
#define  ADC_SS3_FSTAT_OV_MSK  BIT(ADC_SS3_FSTAT_OV_POS)

#define  ADC_SS3_FSTAT_FULL_POS  10U 
#define  ADC_SS3_FSTAT_FULL_MSK  BIT(ADC_SS3_FSTAT_FULL_POS)

#define  ADC_SS3_FSTAT_UV_POS  9U 
#define  ADC_SS3_FSTAT_UV_MSK  BIT(ADC_SS3_FSTAT_UV_POS)

#define  ADC_SS3_FSTAT_EMPTY_POS  8U 
#define  ADC_SS3_FSTAT_EMPTY_MSK  BIT(ADC_SS3_FSTAT_EMPTY_POS)

#define  ADC_SS3_FSTAT_HPTR_POSS  4U 
#define  ADC_SS3_FSTAT_HPTR_POSE  7U 
#define  ADC_SS3_FSTAT_HPTR_MSK  BITS(ADC_SS3_FSTAT_HPTR_POSS,ADC_SS3_FSTAT_HPTR_POSE)

#define  ADC_SS3_FSTAT_TPTR_POSS  0U 
#define  ADC_SS3_FSTAT_TPTR_POSE  3U 
#define  ADC_SS3_FSTAT_TPTR_MSK  BITS(ADC_SS3_FSTAT_TPTR_POSS,ADC_SS3_FSTAT_TPTR_POSE)

/****************** Bit definition for ADC_SS3_DATA register ************************/

#define  ADC_SS3_DATA_DATA_POSS  0U 
#define  ADC_SS3_DATA_DATA_POSE  11U 
#define  ADC_SS3_DATA_DATA_MSK  BITS(ADC_SS3_DATA_DATA_POSS,ADC_SS3_DATA_DATA_POSE)

typedef struct
{
  __IO uint32_t CFG;
  __IO uint32_t SRATE;
  __IO uint32_t CHINV;
  __IO uint32_t GAINL;
  __IO uint32_t GAINH;
  __O uint32_t FRF;
  __IO uint32_t SSEN;
  __IO uint32_t SWTRI;
  __O uint32_t IER;
  __O uint32_t IDR;
  __I uint32_t IVS;
  __I uint32_t RIF;
  __I uint32_t IFM;
  __O uint32_t ICR;
  __IO uint32_t DMA;
  uint32_t RESERVED0 ;
  __IO uint32_t SS0_CON;
  __IO uint32_t SS0_MUX0;
  __IO uint32_t SS0_MUX1;
  __IO uint32_t SS0_END;
  __I uint32_t SS0_FSTAT;
  __IO uint32_t SS0_DATA;
  uint32_t RESERVED1[2] ;
  __IO uint32_t SS1_CON;
  __IO uint32_t SS1_MUX0;
  __IO uint32_t SS1_END;
  __I uint32_t SS1_FSTAT;
  __IO uint32_t SS1_DATA;
  uint32_t RESERVED2 ;
  __IO uint32_t SS2_CON;
  __IO uint32_t SS2_MUX0;
  __IO uint32_t SS2_END;
  __I uint32_t SS2_FSTAT;
  __IO uint32_t SS2_DATA;
  uint32_t RESERVED3 ;
  __IO uint32_t SS3_CON;
  __IO uint32_t SS3_MUX0;
  __IO uint32_t SS3_END;
  __I uint32_t SS3_FSTAT;
  __IO uint32_t SS3_DATA;
} ADC_TypeDef;





#endif
